(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the formation of shallow trench isolations in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
The use of shallow trench isolation (STI) for the formation of integrated circuit isolations has grown in the art due to the reduced surface area and improved topology of STI when compared to traditional local oxidation of silicon (LOCOS) schemes. One problem that is encountered in the use of STI is oxide dishing. Oxide dishing occurs, in part, due to pad deformation in the chemical mechanical polish (CMP) process used to planarize the STI structures. It is called dishing because the STI isolation oxide takes on the shape of a dish as the oxide in the trench is thinned by the CMP process. Dishing is especially pronounced on large or wide STI structures because the isolation oxide over these trenches is typically thinner than the oxide deposited over narrow trenches due to topological effects. Narrower STI structures demonstrate little or no dishing. Another problem in the prior art is oxide erosion during the CMP process.
Referring to FIG. 1, a cross-section of a partially completed prior art integrated circuit is shown. A silicon substrate 10 is shown. Two narrow trenches and one wide trench have been etched into the surface of the silicon substrate 10. An isolation oxide layer 14 fills the trenches. A chemical mechanical polish (CMP) was used to polish down the isolation oxide layer 14 to the top surface of the silicon substrate 10 to complete the shallow trench isolations. Following the polish, however, significant dishing 18 occurred over the widest trench. This dishing 18 can cause increased current leakage and decreased gate oxide voltage breakdown. These problems at the active area interface reduce device yield.
One technique used in the prior art to reduce the oxide dishing and erosion problems is the use of dummy lines. In the dummy lines approach, strips of active area are added in sections to reduce the width of the isolation regions and, thereby, to reduce oxide dishing and erosion. Reverse mask may also used to reduce these problems. Unfortunately, both of these approaches add cost to the manufacturing process.
Several prior art approaches disclose methods to create isolation regions in the silicon substrate. U.S. Pat. No. 5,681,776 to Hebert et al discloses a method to form isolation regions where trenches are etched. Dielectric spacers are formed in the trenches. Silicon plugs are grown in the trenches by selective epitaxial growth (SEG). The silicon plugs are then thermally oxidized to entirely convert the silicon into silicon dioxide. An etch down is then performed to remove dielectric layers overlying active regions and to planarize the structure. U.S. Pat. No. 5,087,586 to Chan et al teaches a process to form isolation regions where trenches are formed with dielectric spacers on the sidewalls. SEG layers are formed in the trenches. The SEG layers are thermally oxidized to convert the silicon to silicon dioxide. Additional silicon dioxide is deposited to fill voids. The surface is then planarized by etching down. U.S. Pat. No. 5,223,736 to Rodder discloses a process to form isolation regions by first forming a reduced topography field oxide region. A trench is formed in the field oxide and then a polysilicon plug is selectively deposited in the trench. The polysilicon plug is then thermally oxidized to form a silicon dioxide layer thereover. U.S. Pat. No. 4,942,137 to Sivan et al discloses a process to form isolation regions where a selective trench filling process is used to deposit, for example, polysilicon into an oxide-lined trench. A thermal oxidation is performed to cap the polysilicon fill layer. U.S. Pat. No. 5,731,221 to Kwon shows a process to form isolation regions where a local oxidation of silicon (LOCOS) region is formed. A trench is etched through the LOCOS region. After sidewall spacers are formed inside the trench, a second, deeper trench is etched into the substrate. A silicon dioxide layer is deposited to fill the trench. A chemical mechanical polish (CMP) is performed to planarize the surface. U.S. Pat. No. 5,424,240 to Han teaches a process to form isolation regions where a trench is etched and filled with polysilicon. After a CMP step, sidewall spacers are formed over the polysilicon and are then used as an etching mask for an etch into the polysilicon of a second, deeper trench. The polysilicon is then thermally oxidized to completely convert the polysilicon into silicon dioxide. U.S. Pat. No. 5,436,190 to Yang et al discloses a process to form isolation regions where a trench is etched into the silicon substrate. Sidewall spacers are formed in the trench. A polysilicon layer is deposited to fill the trench. A CMP step is performed to planarize the polysilicon. The sidewall spacers are then removed. The polysilicon is thermally oxidized to form a silicon dioxide layer to encapsulate the polysilicon plug.